This invention relates to the field of data processing. More particularly, this invention relates to digital adder circuits used within data processing systems.
Addition is one of the most important arithmetic operations to optimize as it is frequently performed within data processing systems. A problem with producing high speed adder circuits is that the high order bits of the result are logically and physically dependent upon the carry out values from the low order bits. In other words, the carry out from the top bit of the adder is a function of every input bit. Consequently, addition operations tend to be relatively slow.
Considerable effort has been expended for decades to address the problem in order to design and develop adder circuits that are capable of operating at high speed. To that end, various addition algorithms have been developed that include adders using maximally parallel-prefix circuits. While such maximally parallel-prefix adders are a great improvement over prior designs, given the extreme focus on improving processor cycle times, there is a continuing need to reduce the time required to produce a result from an add operation.